Semiconductor memory, method of testing semiconductor memory and method of manufacturing semiconductor memory

ABSTRACT

Testing circuits each including a comparator for comparing data read from semiconductor memories to be tested with expected value data and thereby detecting coincidences/non-coincidences, and a counter for counting the number of non-coincidences detected are provided on a printed board for burn-in or within semiconductor memories to be tested. The semiconductor memories can be tested by the testing circuits respectively.

TECHNICAL FIELD

The present invention relates to a semiconductor memory, a method oftesting the same, and a method of manufacturing the same, andparticularly to a technology effective for application to testing andmanufacture of an electrically programmable and erasable nonvolatilesemiconductor memory like a flash memory, and an electricallyprogrammable and erasable nonvolatile semiconductor memory with a testcircuit built therein.

BACKGROUND ART

As a method of testing a semiconductor memory, there is generallyprovided a method of generating test pattern data by a test devicecalled a memory tester, inputting the test data to a memory to therebyperform its writing, next reading the written data from the memory,comparing the data with an expected value, and thereby determining thememory as defective when they do not coincide with each other.

In a volatile semiconductor memory such as a DRAM (Dynamic Random AccessMemory), an SRAM (Static RAM) or the like, a so-called repair technologybased on a redundant circuit system has been established in which aspare memory column or memory row is provided and when a fail bit isdetected, its corresponding substitution is performed. In anelectrically programmable and erasable nonvolatile semiconductor memorytypified by a flash memory, contrary to the above, there is known atechnology for configuring a system in such a manner that a failureaddress is detected by testing, and the detected non-failure/failureinformation is stored in a memory array and provided for a user, and theuser avoids a fail bit through the use of the non-failure/failureinformation and makes use of a normal bit alone.

Further, in the volatile semiconductor memory such as the DRAM, SRAM orthe like, there has been proposed the invention related to asemiconductor memory wherein a test circuit called an ALPG (AlgorithmicMemory Pattern Generator) for generating test patterns (addresses anddata) of a memory circuit in accordance with a predetermined algorithmand performing its test is mounted on a semiconductor chip equipped withthe memory circuit (International Publication WO98/47152).

Such a test technology of ALPG system can be also applied to anonvolatile semiconductor memory. Since, however, the flash memory orthe like needs a mechanism for detecting the failure address by testingand storing the detected non-failure/failure information in the memoryarray as described above, it has been considered that the flash memoryor the like encounters difficulties in providing the test circuit on thechip and performing its testing.

On the other hand, a test placed under a high temperature called aburn-in test or an aging test for detecting potential defective units inaddition to a tester-based inspection at a wafer stage has been alsoperformed upon testing of the semiconductor memories including thenonvolatile memory such as the flash memory or the like as well as theDRAM and SRAM. The burn-in test is performed while mounting several tensto several hundreds of memories each placed in a state of beingassembled into a package, onto a printed board called a burn-in board,collectively inserting the board into a heating chamber in the form ofseveral tens of sheets and applying test patterns from a control device.

The nonvolatile semiconductor memory encounters difficulties instabilizing write and erase characteristics in the case of the presentprocess technology. Therefore, a write and erase-repeated write/erasecycle test unexecuted upon testing of the volatile semiconductor memorysuch as the DRAM (Dynamic Random Access Memory), the SRAM (Static RAM)or the like, has been performed within a burn-in apparatus.

FIG. 10 shows a procedure for testing a conventional nonvolatilesemiconductor memory after the assembly thereof into a package. As shownin the same drawing, memories subsequent to the completion of anassembly step of Step S1 are shifted to a burn-in step (Step S2), wherethey are respectively mounted onto a burn-in board and subjected to aburn-in test in normally several hundreds of units over 10 hours or so.Further, a write and erase-repeated write/erase cycle test is performedwithin the burn-in apparatus (Step S3). Afterwards, the procedureproceeds to a sorting or selection step (Step S4) using a memory tester,where a DC test, an AC test and a function test, etc. are performed,whereby only ones judged as non-defective are shipped.

However, the conventional test method is accompanied by a problem thatsince the tests using the memory tester can be performed only in a fewor several tens of units, they are inefficient as compared with theburn-in apparatus capable of performing tests in several thousands ofunits, and since an expensive tester capable of performing the functiontest is required in the selection step in Step S4, the rate of a testcost taken up in a product unit price becomes so high.

Described specifically, the cost of the tester capable of performing thefunction test takes several tens of times as much in cost as the mostexpensive device with a test function, of a tester and a burn-inapparatus capable of performing a DC test and an AC test alone. Sincethe conventional test method makes use of such an expensive tester andcan be executed only in the few or several tens of units, the number oftesters is limited even if the efficiency of a manufacturing process ismade high. Therefore, the time required to perform each test by thetester was brought into a bottleneck, so that production efficiency wasremarkably reduced. Since the number of expensive testers must beincreased to increase the number of memories testable per unit time, aproblem arises in that a huge or tremendous capital investment isrequired.

An object of the present invention is to provide a test technologycapable of testing a nonvolatile semiconductor memory without using suchan expensive tester as to be capable of performing a function test.

Another object of the present invention is to provide a test technologycapable of increasing the number of nonvolatile semiconductor memoriescapable of simultaneously performing a function test.

A further object of the present invention is to provide a testtechnology capable of causing a nonvolatile semiconductor memory toperform its self-test without increasing a chip size so much.

The above, other objects and novel features of the present inventionwill become apparent from the description of the present specificationand the accompanying drawings.

DISCLOSURE OF THE INVENTION

Summaries of representative ones of the inventions disclosed in thepresent application will be described as follows:

A method of testing a plurality of semiconductor memories to be tested,according to the present invention, is characterized by mounting theplurality of semiconductor memories on a printed board or a test boardequipped with a plurality of sockets in which the plurality ofsemiconductor memories are mountable, and testing circuits eachincluding a comparator for comparing data read from the semiconductormemories with expected value data and thereby detectingcoincidences/non-coincidences therebetween and a counter for countingthe number of the detected non-coincidences, connecting the printedboard to a connector lying within a heating chamber of a burn-inapparatus, simultaneously testing the plurality of semiconductormemories by the testing circuits while updating addresses, and countingthe number of addresses at which failures are detected, by the counterand outputting the result of counting thereby.

According to the above configuration, a plurality of semiconductormemories mounted on the same board can be simultaneously tested within aburn-in apparatus by testing circuits on a printed board and thedetected result of failure can be outputted. It is therefore possible toeliminate the use of such an expensive tester as to be capable ofperforming a function test and test a large number of semiconductormemories simultaneously. Consequently, the cost taken for testing can belowered, and the amount of a capital investment for shorting the timerequired to perform testing can be reduced.

Preferably, failure information obtained by ORing a previous result offailure determination read from storing means for storing a result offailure determination based on the result of comparison by thecomparator with a result of failure/non-failure determination based onthe result of comparison by the comparator is stored again in thestoring means. Thus, since a plurality of types of tests arecontinuously performed and their results can be stored in the storingmeans, test efficiency is enhanced. Since the failure informationobtained by making ORing with the previous result of failuredetermination is stored in the storing means, the memory or storagecapacity of the storing means for storing the failure information can bereduced and the cost of each testing circuit can be lowered.

Further, preferably, the failure information read from the storing meansfor storing the failure information is counted by the counter lyingwithin each testing circuit after the completion of testing. Thereafter,dummy failure information or determining failure information is suppliedto and counted by the counter, and an overflow signal outputted from thecounter is monitored to make failure/non-failure determination.Consequently, a decision as to whether a product (corresponding to asemiconductor memory configured as a device to be tested) isnon-defective or defective, can be simply performed by a simple testdevice.

Next, a semiconductor memory manufacturing method according to thepresent invention is characterized by mounting semiconductor memoriesobtained by cutting memory chips formed on a wafer and enclosing thesame in packages on a printed board or a test board equipped with aplurality of sockets, and testing circuits each including a comparatorfor comparing data read from the semiconductor memories to be testedwith expected value data and thereby detectingcoincidences/non-coincidences therebetween and a counter for countingthe number of the detected non-coincidences, connecting the printedboard to a connector lying within a heating chamber of a burn-inapparatus, simultaneously testing the plurality of semiconductormemories by the testing circuits while updating addresses afterexecution of a burn-in process or while the burn-in process is beingperformed, thereafter taking out the printed board from within theheating chamber of the burn-in apparatus, performing, by a test device,a test other than the tests executed by the testing circuits, andselecting only the semiconductor memories judged as non-defective by thetwo tests.

According to the above configuration, since a plurality of semiconductormemories mounted on the same board are simultaneously tested within aburn-in apparatus by testing circuits on a printed board and thedetected result of failure can be outputted, the use of such anexpensive tester as to be capable of performing a function test becomesunnecessary. Further, since the time required to perform testing can beshortened owing to the execution of simultaneous testing of a largenumber of semiconductor memories, the manufacturing cost can bedrastically reduced.

Further, a semiconductor memory according to the present invention isone configured in such a manner that a testing circuit including acomparator for comparing data read from a memory circuit to be testedwith expected value data to thereby detect coincidences/non-coincidencestherebetween, and a counter for counting the number of the detectednon-coincidences is formed on the same semiconductor chip as one beingformed with the memory circuit to be tested, the memory circuit istested by the testing circuit while updating addresses, the number ofaddresses at which failures are detected, is counted by the counter, andthe result of counting thereby is capable of being outputted to theoutside.

According to the above configuration, the memory circuit is testedwithout using a high-performance tester, so that the presence or absenceof each fail bit can be recognized. Thus, the cost taken for testing canbe reduced, and a large number of semiconductor memories can be testedsimultaneously using a burn-in apparatus or the like, whereby the timerequired to perform testing can be greatly shortened.

Here, preferably, a result-of-determination storage circuit for storinga result of failure determination based on a result of comparison by thecomparator is formed on the same semiconductor chip as one being formedwith the memory circuit to be tested, together with the testing circuit.Thus, since there is no need to store the result of testing in anexternal test device, the management of the test result and the processof product selection or the like based on the management can be easilyperformed.

Each of word lines for the result-of-determination storage circuit maybe configured so as to be selected by a select signal of an addressdecoder for selecting each word line in a memory array of the memorycircuit, and the result of failure determination based on the result ofcomparison by the comparator may be configured so as to be stored in theresult-of-determination storage circuit in association with each memoryrow of the memory array to be tested. Thus, when theresult-of-determination storage circuit for storing the result offailure determination is formed on one semiconductor chip together withthe memory circuit and testing circuit, circuit's simplification isenabled and a substantial increase in chip size can be suppressed.

Further, the result-of-determination storage circuit is provided at partof the memory circuit to be tested. Consequently, further circuit'ssimplification is enabled and an increase in chip size can besuppressed. Further, the result-of-determination storage circuit can bebuilt in a chip without any need to add a new step in a process.

Preferably, information obtained by ORing a previous result of failuredetermination read from the result-of-determination storage circuit witha result of failure/non-failure determination based on the result ofcomparison by the comparator is configured so as to be stored in theresult-of-determination storage circuit. Thus, even when a plurality oftypes of tests are performed, the memory capacity of theresult-of-determination storage circuit for storing their resultstherein needs not to increase. It is therefore possible to realize asemiconductor memory high in reliability and small in chip size.

Further, preferably, the counter for counting the number of failureaddresses is configured so as to count the failure information read fromthe result-of-determination storage circuit. Thus, since the counting ofthe number of failure addresses may be once even when a plurality oftypes of tests are performed, the time required for determination isshortened.

Further, the counter may be configured so as to count the failureinformation read from the result-of-determination storage circuit andoutput an overflow signal when the counter counts subsequently-inputteddummy failure information or determining failure information and countsthe same up to a predetermined number. Thus, since there is no need todetermine the number of failure addresses, and the overflow signal maysimply be monitored, the burden on a test device for making a decisionis less reduced.

When the memory circuit to be tested comprises nonvolatile memoryelements, the result-of-determination storage circuit may be made ofvolatile memory elements. Since the storage circuit made of the volatilememory elements is short in write time as compared with the storagecircuit comprising the nonvolatile memory elements, an increase in testtime can be suppressed where the storage circuit for storing the resultof determination is built in a chip.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a schematic configuration of a burn-inboard to which the present invention is applied;

FIG. 2 is a block diagram illustrating a configuration example of a testcircuit;

FIG. 3 is a flowchart showing a whole test procedure of a flash memoryplaced in the burn-in board to which the present invention is applied;

FIG. 4(A) is a flowchart illustrating a procedure for reading data froma flash memory employed as a device tested upon a burn-in test, and FIG.4(B) is a flowchart showing a procedure for writing data into anon-defective or failure address of the tested device;

FIG. 5 is a flowchart showing a procedure for readingfailure/non-failure information from a failure address storage memoryupon the burn-in test and performing its counting process;

FIG. 6 is a block diagram illustrating a more specific configurationalexample of a test circuit;

FIG. 7 is a block diagram showing an embodiment in which a test circuitis configured using an FPGA;

FIG. 8 is a block diagram depicting another configurational example inwhich a test circuit is configured using an FPGA;

FIG. 9 is a block diagram showing another configurational example of atest circuit;

FIG. 10 is a flowchart showing a test procedure of a conventional flashmemory;

FIG. 11 is a flowchart illustrating a test procedure of a flash memoryto which the present invention is applied;

FIG. 12 is a block diagram showing a schematic configuration of a flashmemory to which the present invention is applied; and

FIG. 13 is a block diagram depicting another embodiment of a flashmemory to which the present invention is applied.

BEST MODE FOR CARRYING OUT THE INVENTION

Preferred embodiments of the present invention will hereinafter bedescribed based on the accompanying drawings.

A schematic configuration of a test board used as a burn-in board formounting a plurality of semiconductor memories thereon and insertingthem in a burn-in apparatus and allowing them to be testedsimultaneously, to which the present invention is applied, is shown inFIG. 1.

In FIG. 1, reference numeral 100 indicates a burn-in board comprising aprinted wiring board, reference numerals 200 indicate devices to betested, such as a flash memory used as an electrically programmable anderasable nonvolatile semiconductor memory to be tested, etc., andreference numerals 110 indicate test circuits which respectivelygenerate signals for the tested devices 200 in response to controlsignals supplied from a device placed outside the board, and take in andprocess signals outputted from the tested devices 200.

In the burn-in board 100 according to the present embodiment as shown inFIG. 1, the test circuits 110 each brought into semiconductor integratedcircuit form, and failure-address storing semiconductor memories 120like RAMs each storing a test result are alternately disposed in thecenter of the board by a plural number (nine in the drawing) in a singlehorizontal row. The tested devices 200 are respectively disposed on bothsides (upper and lower sides in the drawing) of the test circuits 110 bya predetermined number (four in the drawing).

Connection terminal rows 130 are formed at one side (left side in thedrawing) of the burn-in board 100. The connection terminal rows 130 areinserted into their corresponding connectors (slots) provided within aheating chamber of the unillustrated burn-in apparatus to make itpossible to transmit and receive signals between a control device on theburn-in apparatus side and each test circuit 110 on the board. Further,a device protection circuit 140 constituted of resistors, capacitors,fuses, etc. which is used to protect the tested devices 200 from a surgevoltage or the like, is provided on the connection terminal rows 130side of the burn-in board 100.

The test circuits 110 each brought into the semiconductor integratedcircuit form, and the failure-address storing semiconductor memories 120like RAMs each storing the test result respectively have externalterminals directly connected onto the burn-in board 100 by solder or thelike, whereas the tested devices 200 are detachably inserted and mountedin their corresponding sockets (not shown) provided on the burn-in board100.

Along with the above, wiring patterns (not shown) for connectingcorresponding terminals of eight sockets placed in a row as viewed in avertical direction and corresponding terminals of the central testcircuits 110 respectively are formed on the board. One test circuit 110simultaneously applies the same signal to the eight tested devices 200placed in one row. Upon reading of data, signals outputted from theeight tested devices 200 placed in one row are configured so as tocollect into the corresponding center test circuit 110. Further, thesame signal is simultaneously transmitted from the control device on theburn-in apparatus side even to the nine test circuits 110 placed on theboard. Signals indicative of results tested on the respective testeddevices 200 are configured so as to be outputted in parallel from therespective test circuits 110 to the control device on the burn-inapparatus side.

Incidentally, although not restricted in particular, on-board wiringsare formed in such a manner that memory control signals such as a writecontrol signal WE, a chip select signal CE, an output enable signal OE,etc., corresponding to part or some of the signals supplied from thecontrol device on the external burn-in apparatus side to the burn-inboard 100 are directly supplied to the tested devices 200 without viathe test circuits 110.

FIG. 2 shows a schematic configuration of one embodiment of a testcircuit 110 provided on the burn-in board 100.

The test circuit 110 according to the present embodiment is configuredso as to include a write control circuit 111 which outputs an addresssignal ADD and write data Din supplied from the control device on theburn-in apparatus side to the burn-in board 100 to the correspondingtested device 200 with timing suitable for the semiconductor memorycorresponding to a device to be tested and controls the interior of thecorresponding test circuit, a data comparator 112 which compares readdata Dout read from the tested device 200 with an expected value EXDsupplied from the control device on the burn-in apparatus side andthereby determines coincidence/non-coincidence between the two, anaddress latch 113 which takes in or captures address signals (wordaddresses) supplied from the control device on the burn-in apparatusside upon reading and retains them therein, a failure OR circuit 114which makes ORing with the result of coincidence/non-coincidence ofprevious read data, and a counter 115 which counts the number ofdefective or failure addresses.

Incidentally, in the present embodiment, the comparison between the readdata and the expected value by the comparator 112 is configured so as tobe performed with sectors, i.e., memory cells connected to the same wordline and placed in the same row as units. Thus, if a fail bit existswithin each of the sectors even one, then the corresponding sector isregarded as a fail or bad sector. The number of failure addresses eachindicative of the position of the bad sector, i.e., the number of badsectors is counted by the counter 115.

A failure-address storage memory 120 for storing a test result comprisesa memory for inputting and outputting data in 1-bit units, which has thesame number of bits as the number of sectors of a flash memory of thetested device 200, or storage or memory capacity greater than or equalto it, and is configured so as to be accessed by a word address suppliedfrom the control device on the burn-in apparatus side to the testeddevice 200, thereby causing the corresponding sector of the testeddevice 200 and the corresponding address of the failure-address storagememory 120 to correspond at a rate of 1:1.

Thus, when 1-bit information indicative of failure/non-failure of asector corresponding to a given address of the failure address storagememory 120 is stored therein, the corresponding address of the failureaddress storage memory 120 in which the information indicative of“failure” has been stored, indicates an address for a bad sector in thetested device 200. Accordingly, the failure address storage memory 120is capable of regarding a failure address of each tested device as beingstored therein.

In the present embodiment, when the failure address storage memory 120is accessed by a word address latched in the address latch 113, dataexpressed in its corresponding bit is read and supplied to the failureOR circuit 114, where the data and a signal indicative of the result ofcomparison by the comparator 112 are ORed, after which the result ofORing is written back into the same address of the failure addressstorage memory 120.

Further, the test circuit 110 according to the present embodiment isconfigured in such a manner that the number of bits corresponding to,for example, a logical “1” indicative of a failure, which have beenstored in the failure address storage memory 120, is counted by thecounter 115, an overflow signal OVF indicating overflowing of thecounter 115 is outputted to the control device on the burn-in apparatusside via an input/output line I/O, and the supply of data (or address)from the write control circuit 111 to the tested device 200 isprohibited by the bits indicative of the failure, which have been storedin the failure address storage memory 120.

The control device on the burn-in apparatus side makes use of thecounter 115 and monitors the overflow signal OVF outputted therefrom,thereby making it possible to recognize that the number of failureaddresses in the corresponding tested device has exceeded an allowablenumber. Incidentally, the overflow signal OVF may be configured so as tobe outputted to the control device on the burn-in apparatus side via thefailure OR circuit 114 as will be described later. The signal indicativeof the failure/non-failure outputted from the failure OR circuit 114,and the information indicative of the result of failure determinationread from the failure address storage memory 120 may also be configuredso as to be outputted to the control device on the burn-in apparatusside via the input/output line I/O.

One example of a test procedure of the tested device 200, using the testcircuit 110 constructed in the above-described manner will next bedescribed using FIG. 3.

When a test is started, the failure address storage memory 120 is firstinitialized (Step S31). Here, the initialization means that stored dataof all bits of the failure address storage memory 120 are set to alogical “0” indicative of “non-failure”. When, for example, the flashmemory is a device in which a command register, a status register, etc.provided thereinside need to be initialized, the tested device 200 isalso initialized. This initialization can be performed by, for example,the control signals WE, CE, OE, etc. directly supplied from the controldevice of the burn-in apparatus to the flash memory.

When the initialization of the failure address storage memory 120 iscompleted, an erase test is first performed (Step S32). The erase testmeans that all the memory cells in the flash memory are respectivelybrought to an erase state (e.g., a state in which a threshold is high).With a block constituted of a predetermined number of sectors as a unit,for example, data in memory cells for all sectors in the block aresimultaneously erased. After the erase operation, verify reading isperformed (Step S33). The erase verify reading is carried out in sectorunits.

Data read by the verify operation is compared with an expected value(all “0” or all “1”). When a sector having an erase failure exists, alogical “1” indicative of “failure” is written into the correspondingaddress of the failure address storage memory 120. The erase state maycorrespond to a state in which the threshold of each memory cell is low.The logical “0” of each stored data may correspond to the erase state ofthe memory cell, or the logical “1” of each stored data may correspondto the erase state of the memory cell. The present embodiment will bedescribed below on condition that the logical “0” of the stored data hasbeen associated with the erase state of the memory cell.

FIG. 4(A) shows a detailed operation procedure at the verify reading.Upon the read operation, a command (read command in this case) relativeto the corresponding tested device is first directly supplied from thecontrol device on the burn-in apparatus side by each of device controlsignals WE, CE, OE, etc. (Step S51). Next, an address ADD is inputted tothe test circuit 110 (Step S52). This address ADD is supplied to thetested device 200 through the write control circuit 111 and taken in theaddress latch 113 lying within the test circuit 110. The address latchedin the address latch 113 is supplied to the failure address storagememory 120, and a signal indicative of reading separately from theaddress is supplied from the control device on the burn-in apparatusside to the failure address storage memory 120.

A wait for reading of data from the tested device 200 is subsequentlyexecuted (Step S53). During this period, the data (defective or failureinformation) read from the failure address storage memory 120 is sent tothe failure OR circuit 114. In the following Step S54, an expected valueEXD is transmitted from the control device on the burn-in apparatusside, and the data read from the tested device 200 is supplied to thecomparator 112, where a comparison between the expected value and thedata is made. The result of comparison is outputted to the failure ORcircuit 114, which in turns makes ORing with the data read from thefailure address storage memory 120.

The result of this ORing is written into the same address position ofthe failure address storage memory 120 in the following Step S55. Atthis time, the control device on the burn-in apparatus side supplies asignal for instructing the failure address storage memory 120 to performwriting. During this period, the address ADD inputted in Step S52 isretained in the address latch 113. It is judged in the following StepS56 whether the input address is a final address. If it is found not tobe of the final address, then the operation procedure returns to StepS51, where reading for the following address is performed. When it isdetermined in Step S56 that the address is of the final address, then aseries of reading processes for performing erase verify are completed.

Subsequently to the erase verify, a write test based on a first patternlike, e.g., an all “1” pattern is carried out (Step S34 in FIG. 3). Thiswrite test is performed in sector units. Since a specific procedure ofsuch a write test is substantially identical to the verify reading ofFIG. 4(A), the description thereof will be omitted.

When the write test is finished, the verify reading is performedsubsequently (Step S35). This reading is also carried out in sectorunits. However, the present verify reading may be performed afterwriting has ordinarily been effected on all sectors. Alternatively, theverify reading may be performed immediately after writing into eachsector. The above write verify reading is also performed according to aprocedure similar to the flowchart of FIG. 4(A) indicative of the readprocedure for the erase verify.

Then, data read by the verify operation is compared with an expectedvalue (“0” or “1”). When a sector having a write failure exists, alogical “1” indicative of “failure” is written into the correspondingaddress of the failure address storage memory 120. Incidentally, sincethe result of comparison by the comparator 112 and the data read fromthe corresponding failure address storage memory 120 are ORed by thefailure OR circuit 113, the logical “1” indicative of “failure” iswritten into the corresponding address again as to each sector alreadyjudged as faulty in the erase verify of Step S33.

When the write test based on the pattern A and the verify reading arecompleted, an erase test and verify are performed again (Steps S36 andS37). Since the erase test and verify are identical to Steps S32 andS33, their detailed description will be omitted.

Thereafter, a write test based on a second pattern B like, e.g., achecker pattern different from the pattern A, and verify reading areperformed (Steps S38 and S39). When a sector judged as being existent ina write failure exits, a logical “1” indicative of “failure” is writteninto the corresponding address of the failure address storage memory120. Afterwards, the ease test is performed again. Thus, when writetests based on a plurality of test patterns prepared in advance, and thefinal erase test (Step S40) are finished, the writing of data(corresponding to data of a logical “1” when an erase state is regardedas a logical “0”) into a sector of a tested device judged to be “good”is performed (Step S41). This writing into the non-failure address isautomatically performed by the test circuit 110 employed in theembodiment according to a procedure indicative of a flowchart shown inFIG. 4(B).

Namely, a write command is first supplied from the control device on theburn-in apparatus side to the corresponding tested device 200 (StepS21). Next, an address ADD is inputted to the corresponding test circuit110 (Step S22). This address ADD is supplied to the tested device 200via the write control circuit 111 and taken or brought in the addresslatch 113 lying within the test circuit 110. The latched address issupplied to the failure address storage memory 120. Further, a signalfor giving read instructions as distinct from the address is suppliedfrom the control device on the burn-in apparatus side to the failureaddress storage memory 120.

Subsequently, the supply of write data from the control device on theburn-in apparatus side to the tested device 200 is performed (Step S23).During this period, the data (defective or failure information) readfrom the failure address storage memory 120 is sent to the write controlcircuit 111. In the following step S24, a write start command issupplied from the control device on the burn-in apparatus side to thetested device 200.

At this time, data indicative of “non-failure” or “failure” has beensupplied from the failure address storage memory 120 to the writ controlcircuit 111 in association with the address as described above. Amasking gate MSK masks write data supplied to the tested device 200according to the data. Described specifically, when data indicative of“failure” is read from the failure address storage memory 120, thesupply of write data (or address) to the tested device 200 is blocked orcut off.

Thus, when the data indicative of “failure” is read, the writing of datainto the corresponding sector of the tested device 200 is prohibited.When the data indicative of “non-failure” is read, the writing of data“1” into the corresponding sector of the tested device 200 is performed.Therefore, when the data is determined by reading of data from thecorresponding memory after the completion of testing, the sector can beeasily judged as a normal sector if the data “1” has been written. Whenthe read data is “0”, the sector can be easily determined to be a sectorincluding a fail bit.

The above processes (Steps S21 through S24) are repeated until theaddress reaches the final address while the address is being updated(+1) in Step S25. When the address is determined to be the final addressin Step S26, the process of writing data into the correspondingnon-failure address of the tested device is finished.

When the writing into the non-failure address in Step S41 is completedwith respect to all sectors of the tested device, a process for making adecision (called “MGM determination”) as to whether the number offailure addresses exceeds the number of failure addresses, which isallowable for the tested device is performed through the use of thecounter 115 in the present embodiment (Step S42). In the following StepS43, a check is made as to whether the overflow signal OVF is outputtedfrom the counter 115, to thereby make a decision as to a non-defectiveitem or defective item.

While a nonvolatile memory such as a flash memory is normally allowed tohave fail bits, substantial memory capacity is reduced when fail bitsare too many, and hence it exerts an influence even on the reliabilityof each device. Therefore, the fail bits (the number of sectorsincluding fail bits accurately) are normally allowable up to theallowable number. In Step S42, the number of the failure addressesstored in the failure address storage memory 120 upon the tests of StepsS32 through S40 is counted by the counter 115. Further, when the numberof the failure addresses is over the allowable number, the counter 115is operated so as to output the overflow signal OVF, so that anon-failure/failure decision as to each tested device is made.

The details of the non-failure/failure procedure adopted for the presentembodiment will be described below using a flowchart of FIG. 5.Incidentally, the assumption is now made that before a process to beexecuted according to the flowchart is started, non-failure/failureinformation lying within the respective tested devices in Steps S32through S40 have been stored in the failure address storage memory 120and the counter 115 has been cleared.

The control device of the burn-in apparatus sends a leading address forthe failure address storage memory 120 to the corresponding test circuit110 and causes the address latch 113 to latch it therein (Step S61).Next, the failure address storage memory 120 is accessed by the latchedaddress to read the stored non-failure/failure information (Step S62).In doing so, the failure information is supplied to the counter 115. Ifthe failure information indicates “failure”, then the counter 115 iscounted up. If the failure information indicates “non-failure”, then thecounter 115 is not counted up.

Then, the control device of the burn-in apparatus increments the addressby (+1) (Step S63). It is determined whether the address has reached amaximum value, i.e., a final address of the failure address storagememory 120 (Step S64). If the address is found not to reach the finaladdress, then the procedure returns to Step S61, where the updatedaddress is supplied to the test circuit 110 to read the followingnon-failure/failure information from the failure address storage memory120. By repeating the above operations, the counter 115 is counted upaccording to the non-failure/failure information. It is determined inStep S64 whether the final address is reached. When the procedureproceeds to the next Step S65, a count value of the counter 115 justcoincides with the number of failure addresses (failure or bad sectors)included in the corresponding tested device.

In Step S65, dummy failure information or determining failureinformation is sent from the control device of the burn-in apparatus tothe counter 115 by a prescribed number to count up the counter 115. Now,the prescribed number is a value (Cmax−Pmax) obtained by, when thenumber of failure addresses allowable for each tested device is assumedto be Pmax, subtracting the maximum allowable number Pmax of the failureaddresses from the maximum count value Cmax of the counter. If the countvalue of the counter 115 immediately prior to the transmission of thedummy failure information is smaller than the number Pmax of the failureaddresses allowable for the tested device, then the count value of thecounter 115 does not reach the maximum count value Cmax even if thedummy failure information is transmitted by the prescribed number.Therefore, no overflow signal OVF is outputted from the counter 115.

On the other hand, when the count value of the counter 115 immediatelyprior to the transmission of the dummy failure information is largerthan the number Pmax of the failure addresses allowable for the testeddevice, the dummy failure information is transmitted by the prescribednumber so that the count value of the counter 115 exceeds the maximumcount value Cmax. Therefore, the overflow signal OVF is outputted fromthe counter 115. Thus, the control device on the burn-in apparatus sidemonitors the overflow signal OVF outputted from the counter 115 tothereby make it possible to detect whether the number of the failureaddresses included in the corresponding tested device exceeds themaximum allowable number Pmax. When no overflow signal OVF is outputtedeven if the dummy failure information is transmitted by the prescribednumber, the corresponding tested device can be judged to be a“non-defective item”. When the overflow signal OVF is outputted, thecorresponding tested device can be determined as a “defective item”.

Incidentally, it is desirable that a memory in which data is inputtedand outputted in 8-bit units, is used as a failure address storagememory, the comparator 112, the counter 115, etc. are provided by anumber corresponding to the number (eight) of devices tested by one testcircuit 110, and signal lines for respectively separately outputtingoverflow signals OVFs produced from the respective counters 115 to thecontrol device on the burn-in apparatus side are provided on the burn-inboard. Thus, even if the tested devices on the board are simultaneouslytested, it is possible to easily determine which tested device is anon-defective item or which tested device is a defective item.

FIG. 6 shows a more detailed configuration of the test circuit 110 shownin FIG. 2. In FIG. 6, circuit blocks each having the same function asFIG. 2 are respectively identified by the same reference numerals andthe description of certain common blocks will be omitted.

As shown in FIG. 6, the failure OR circuit 114 comprises a latch LATwhich latches non-failure/failure information read from the failureaddress storage memory 120, an OR logic gate ORG which inputs acoincidence/non-coincidence determination signal sent from thecomparator 112 side, and the non-failure/failure information taken inthe latch LAT and read from the failure address storage memory 120, anda transfer gate TMG which transfers the output of the OR logic gate ORGto the failure address storage memory 120 or blocks its output. Aselector SELL for selectively supplying the output of the comparator 112or an overflow signal OVF outputted from the counter 115 to the failureOR circuit 114 is provided between the comparator 112 and the failure ORcircuit 114. The selector SELL is controlled so as to selectively outputany one of the inputs in response to a switching control signal CNSsupplied from the control device on the burn-in apparatus side.

Further, the embodiment shown in FIG. 6 is provided with a selector SEL2capable of selectively supplying an address ADD and write data Dinsupplied from the control device on the burn-in apparatus side to thecorresponding tested device, and a mask gate MSK capable of prohibitingthe transfer of the address ADD and the write data Din. The address ADDand the write data Din supplied from the burn-in apparatus side areinputted to one input terminal of the mask gate MSK. The readinformation (non-failure/failure information) outputted from failureaddress storage memory 120, which has been latched in the latch LAT inthe failure OR circuit 114, is inputted to the other input terminal ofthe mask gate MSK, whereby the transfer of the data is prohibited orpermitted according to the non-failure/failure information. The outputof the mask gate MSK is inputted to a second input terminal of theselector SEL2. An input data select signal supplied from the controldevice on the burn-in apparatus side is applied to a control terminal ofthe selector SEL2.

When the address ADD is inputted from the control device on the burn-inapparatus side as input data, and the input data select signal IDSindicates an “address”, the selector SEL2 selects a signal inputted to afirst input terminal and outputs it to the corresponding tested deviceside. On the other hand, when the write data Din is inputted from thecontrol device on the burn-in apparatus side as input data, and theinput data select signal indicates “write data”, the selector SEL2selects the signal inputted to the second input terminal and outputs itto the tested device side.

Since, at this time, the mask gate MSK prohibits the transfer of datawhen the read information (non-failure/failure information) sent fromthe failure address storage memory 120, which is inputted to the otherinput terminal of the mask gate MSK, indicates a “failure”, no writedata is outputted to the tested device even if the write data isinputted from the control device on the burn-in apparatus side.Accordingly, data is written or not written into each sector lyingwithin the tested device 200, corresponding to an address associatedwith the presence or absence of a failure, depending on the presence orabsence of the failure. Incidentally, the mask gate MSK may prohibit thesupply of an address or a command according to the non-failure/failureinformation as an alternative to the prohibition of the supply of thewrite data according to the non-failure/failure information.

Further, there are provided in FIG. 6, a timing generator TMG whichgenerates timing signals for operating respective portions lying withinthe test circuit 110, based on a test control signal and a clock signalCLK supplied from the control device on the burn-in apparatus side, anda decoder DEC which decodes an output select signal OST supplied fromthe control device on the burn-in apparatus side to generate an outputpermission or enable signal FM_OE for the failure address storage memory120 or an output permission or enable signal TG_EN for the transfer gateTMG in the failure OR circuit 114. The write control circuit 111 shownin FIG. 2 comprises the selector SEL2, mask gate MSK, timing generatorTMG and decoder DEC.

In FIG. 6, the non-failure/failure information read from the failureaddress storage memory 120 is inputted to a clock terminal of thecounter 115 through an AND logic gate AGT controlled by a timing signalCNT-CLK supplied from the timing generator TMG. A clock pulse issupplied or unsupplied to the counter 115 according to thenon-failure/failure information stored in the failure address storagememory 120, where the number of failure addresses is counted. Thecounter 115 is configured so as to perform a count-up operation evenaccording to dummy non-failure/failure information supplied from thecontrol device on the burn-in apparatus side via the input/output lineI/O. Incidentally, in FIG. 6, a circuit surrounded by a dashed line UNTis provided by the number of tested devices (eight) and other circuitsare used as common circuits.

On the other hand, since the test circuits 110 shown in FIGS. 2 and 6are all constituted of logic circuits, each of them can be configuredusing an LSI capable of constituting arbitrary logic, called an FPGA(Field Programmable Gate Array). FIG. 7 shows a system configurationalexample of a burn-in board where a test circuit is configured using anFPGA.

In FIG. 7, reference numeral 110 indicates a test circuit comprised ofthe FPGA, reference numeral 120 indicates a failure address storagememory which stores the result of failure determination, and referencenumerals 200 indicate devices to be tested, respectively. In the presentembodiment, comparators, counters, etc. corresponding to the eighttested devices 200 are provided within one test circuit 110. The failureaddress storage memory 120 is also configured so as to store failureinformation corresponding to the eight tested devices 200 singly. Thus,the failure address storage memory 120 may preferably make use of anSRAM capable of inputting and outputting 8-bit data simultaneously.

In FIG. 7 as well, reference numeral 150 indicates a ROM (Read OnlyMemory) which stores logic-configured data of the FPGA. The FPGA isconfigured such that a large number of variable logic cells capable ofconstituting arbitrary logic circuits, such as OR gates, AND gates,flip-flops, etc. are disposed inside a chip in matrix form, and isprovided therearound with an orthogonal wiring group which makes itpossible to connect between arbitrary variable logic cells, and avariable wiring switch group which makes it possible toconnect/disconnect crossed arbitrary wirings. The ROM 150 storesinformation for determining the logic of each variable logic cell in theFPGA, and on and off information about variable wiring switches.

Incidentally, although not restricted in particular, the ROM 150 isprovided in common with the test circuits 110 comprising a plurality(e.g., nine) of FPGAs placed on a board. Since a 1-chip LSI (ModelNumber: EPF10K130E) having a 130K gate scale has been provided from,e.g., Altera Corporation as the FPGA having the function referred toabove, the corresponding test circuit 110 according to the embodimentcan be constructed using the LSI.

On the other hand, as the FPGA, there is also provided one wherein a RAMis built in a chip. A test circuit mounted on a burn-in board may beconfigured using an FPGA with such a RAM built therein. FIG. 8 shows aconfigurational example of a test circuit using such an FPGA with thebuilt-in RAM. In FIG. 8, designated at reference numeral 400 is an FPGA.

In the present embodiment, a RAM 420 built in the FPGA 400 is utilizedas a failure address storage memory which stores failure informationabout a device to be tested. Since the present test circuit is similarin other configurations to the test circuit 110 according to theembodiment shown in FIG. 2, the same circuit blocks are respectivelyidentified by the same reference numerals, and the description ofcertain common blocks will be omitted. Even in the present embodiment,write control circuits 111, comparators 112, failure OR circuits 114,and counters 115 are respectively provided by numbers corresponding tothe number (e.g., eight) of devices to be tested by one FPGA, and othercircuits are used as common circuits.

FIG. 9 shows another embodiment of a test circuit 110 provided on aburn-in board. The test circuit 110 according to the present embodimentis one configured so as to be capable of outputting an overflow signalof a counter 115 to a corresponding tested device 200 via a selectorSEL2 as an alternative to the output thereof to a control device on theburn-in apparatus side. Thus, the number of failure addresses (failureor bad sectors) set every tested devices are written into flash memoriesas their corresponding tested devices after test completion and testingis finished. After the completion of the testing, data for the testeddevices are read, and the number of sectors, i.e., the number of failureaddresses in which failure information have been stored, is determined,so that a decision as to whether each product is good or bad, can bemade.

In the present embodiment, the most significant bit MSB of the counter115 can be supplied to a failure OR circuit 114 via a selector SEL1. Ina manner similar to the above embodiment, a predetermined number ofdummy failure signals are transmitted from the control device, on thebur-in apparatus side to count up the counter 115, thereby checking fora change in the most significant bit MSB, whereby it is also possible todetermine whether the number of the failure addresses (bad sectors)included in the corresponding tested device is less than or equal to themaximum allowable number.

Incidentally, an advantage is brought about in that when the testcircuit 110 provided on the burn-in board is comprised of such FPGAs asshown in FIGS. 7 and 8, any change in hardware is not made, and datastored in such a logic-configured information storing ROM 300 as shownin FIG. 7 is simply rewritten, so that the test circuit having such aconfiguration as shown in FIG. 9 can be made up.

A method of testing a flash memory using a burn-in board equipped withthe test circuit according to the above embodiment and a process formanufacturing the same will next be described using a flowchart shown inFIG. 11.

The flash memory after the completion of an assembly step in Step S1 isshifted to a burn-in step (Step S2). In the present embodiment, severalten sheets of burn-in boards 100 equipped with 72 flash memories persheet are inserted into their corresponding connectors lying within aheating chamber of a burn-in apparatus so that a control device on theburn-in apparatus side and test circuits on the board are electricallyconnected. However, the test circuit 110 is left under a hightemperature (about 125° C.) for 8 to 16 hours while remaining in itsdeactivated state upon burn-in of Step S2. Next, a write/erase cycletest in which the control device on the burn-in apparatus siderepeatedly effects writing and erasure on the corresponding testeddevice 200 through its corresponding test circuit 110 on the board, isexecuted (Step S3). While this test can be performed by the burn-inapparatus, the temperature in the chamber is set low.

In the present embodiment, a control signal is thereafter transmittedfrom the control device on the burn-in apparatus side to thecorresponding test circuit 110 on the board, where such an erase test ora predetermined pattern-data write/read test (so-called function test)as described above is executed (Step S4). While this test takes abouttwo hours, it may be performed without heating. Alternatively, it canalso be carried out simultaneously with the burn-in process of Step S1.If the burn-in process of Step S1 and the function test of Step S3 aresimultaneously performed, then a function test time interval can be setto substantially disappear.

The function test of Step S4 may be performed using a simple testerwithout the use of the burn-in apparatus while the corresponding testeddevice 200 is being mounted on the burn-in board 100 equipped with thetest circuit 110. The normal memory tester is very expensive, and thefunction test can be executed about several ten times alone at a time.However, if the burn-in board employed in the above embodiment equippedwith the test circuit is used, then the function test can be carried outusing a more inexpensive simple tester without using a high-leveltester. It is therefore possible to greatly reduce the cost required fortesting.

Incidentally, the process proceeds to a selection step of Step S5 afterthe completion of the function test of Step S4, where a DC test forexamining DC-based test items such as a check for a normal operationwithin a predetermined source voltage range, etc., and an AC test forexamining an AC-based test items such as a check for a proper operationeven where an input signal changes at an intended frequency, etc. areperformed using a memory tester. One judged as being non-defective isselected and shipped. Since the DC test and the AC test are finished inten minutes or so, cost performance is not so degraded even if anexpensive memory tester is used.

In a conventional test process shown in FIG. 10, an expensive memorytester is used after a burn-in process and a function test is alsoperformed as well as a DC test and an AC test as described in Step S14.In addition, the time required to perform such a function test was 1 to2 hours. Therefore, test efficiency and cost performance were sodegraded. However, when the present invention is applied, the batchfunction test may be performed by an inexpensive tester or burn-inapparatus in Step S4, whereas in the selection step of Step S5, only theDC test and AC test may be executed. It is therefore possible to greatlyshorten a time interval required for testing and substantially reduce atest cost too.

Other embodiments of the present invention will next be described usingFIGS. 12 and 13.

The embodiment shown in FIG. 12 is one provided with a self-test circuitsimilar to the test circuit on the burn-in board described in the aboveembodiment.

In the drawing, reference numeral 10 indicates a memory array in whichthe known nonvolatile memory elements each comprising an MOSFET having acontrol gate and a floating gate are disposed in matrix form, referencenumeral 11 indicates an X decoder for selecting one of a plurality ofword lines connected with control gates of memory elements placed in thesame row and applying a predetermined voltage thereto according to anoperation mode, and reference numeral 12 indicates an address registerfor holding or retaining an X address (sector address) decoded by the Xdecoder 11, respectively. The X decoder 11 includes a word drive circuitfor driving one word line in each memory mat to a select level accordingto the result of decoding.

Reference numeral 13 indicates a sense amplifier & data latch capable ofamplifying data read from within the memory array 10 and holding, insector units, write data written into the memory array 10, referencenumeral 14 indicates a Y-system address decoder, reference numeral 15indicates a Y gate (column switch row) for connecting the data register13 selectively turned on and off by the Y decoder 14 to itscorresponding common input/output line 16, reference numeral 17indicates a data register which retains write data captured or broughtfrom outside, reference numeral 18 indicates a Y address counter whichgenerates a sequential Y address for sequentially outputting data inbyte units out of read data corresponding to one sector read by thesense amplifier & data latch 13, and reference numeral 19 indicates amultiplexer for taking in addresses and data from a common input/outputpin I/O on a time-division basis, respectively.

Although not restricted in particular, the flash memory according to thepresent embodiment is provided with a control circuit (sequencer) 20which sequentially forms and outputs control signals for respectivecircuits lying inside the memory in order to interpret each command(instruction) supplied from a control device such as an externalmicroprocessor or the like and execute a process associated with thecorresponding command. The flash memory is configured so as to decode acommand when the command is given and automatically execute itscorresponding process. The control circuit 20 is provided with a ROM(Read Only Memory) in which a series of micro instruction groupsrequired to execute a command, for example are stored, and is configuredsuch that micro instructions are sequentially executed to form controlsignals for respective circuits lying inside a chip. Further, thecontrol circuit 20 includes a status register which reflects itsinternal state.

As control signals inputted to the flash memory according to the presentembodiment from an external CPU or the like, may be mentioned, forexample, a reset signal RES, a chip select signal CE, a write controlsignal WE, an output control signal OE, a command enable signal CDE forindicating the input of data or the input of each address, a serialclock SC for giving a data take-in or fetch timing, etc. Further, theflash memory according to the present embodiment is configured so as tooutput a ready/busy signal R/B indicative of whether accessing isallowed from outside, to the outside according to predetermined bits ofthe status register which reflects the internal state of the memory.

The flash memory according to the present embodiment is provided with acomparator 112 which compares 1-byte data read from the memory array 10and selected by the Y gate 15 with expected-value data inputted fromoutside, a failure OR circuit 114 which takes ORing of the result ofcomparison with the result of coincidence/non-coincidence of previousread data, a counter 115 which counts the number of failure addresses, afailure address storage memory 120 which comprises an SRAM or the likeand stores therein non-failure/failure information detected by a test,and a BIST (Build In Self Test) control circuit 160 which controls testoperations in the chip.

A specific configuration of the failure OR circuit 114 is similar tothat described in the embodiment of FIG. 6. A procedure and contents ofa test by the comparator 112, failure OR circuit 114, counter 115, andfailure address storage memory 120 are also substantially similar toones described in the embodiments of FIGS. 2 and 6. The points ofdifference therebetween reside in that the flash memory according to thepresent embodiment is configured in such a manner that word lines forthe failure address storage memory 120 are simultaneously selected bytheir corresponding select signals of the X decoder 11 for the memoryarray 10, and the result of failure determination by a test circuit isstored in a storage or memory region in the failure address storagememory 120 corresponding to each memory row of the memory array 10, andalso configured such that addresses at a write test and verify aredirectly supplied to the memory array 10 from outside through theinput/output pin I/O.

However, such a write control circuit 111 (input mask circuit MSK,selector SEL2, timing generator TMG and decoder DEC) as shown in theembodiment of FIG. 2 (FIG. 6) may be provided within the chip as part ofa test circuit. As an alternative to the input of testing addresses anddata from outside, the above ALPG for generating the testing addressesand data in accordance with the predetermined algorithm is providedinside the chip, and the memory array 10 may be tested according to thetesting addresses and data generated in the ALPG.

In a manner similar to the above control circuit 20, the BIST controlcircuit 160 employed in the present embodiment is provided with a ROM inwhich a series of micro instruction groups necessary to execute eachcommand, for example, have been stored. The BIST control circuit 160 canbe comprised of a control circuit of a microprogram control system,which sequentially executes micro instructions to form control signalsfor respective circuits lying inside the chip. A command for effecting atest start on the BIST control circuit 160 is configured so as to besupplied from the control circuit 20.

Since commands are originally prepared for the flash memory for thepurpose of its self test, such a flash memory is capable of giving atest start command from an external device through the use of aself-test starting command. A memory free of such a command is alsoconfigured such that non-used combinations of the external controlsignals such as the write control signal WE, the output control signalOE, etc. are used and a data input/output terminal is used to enable theinput of each command code, thus making it possible to give a test startcommand to the BIST control circuit 160. The BIST control circuit 160and the control circuit 20 of the flash memory may be formed integrally.

Further, there can also be provided a dedicated interface for the BISTcontrol circuit 160. In such a case, a TAP (Test Access Port) defined bythe IEEE1149.1 standard can be utilized. The TAP comprises a bypassregister used upon shifting test data from an input port to an outputport with an interface and a control circuit for a scan test and a BISTcircuit defined by the IEEE1149.1 standard, a data register used when aspecific signal is transmitted to the corresponding circuit, a device IDregister for setting a manufacture identification number inherent in thechip, an instruction register used upon controlling the selection of thedata register and an internal test method, a controller for controllingthe entire TAP circuit, etc. Owing to the setting of the TAP as theinterface, the number of electrode pads for connecting to the externaldevice for the purpose of data rewriting may be several.

Incidentally, although not shown in FIG. 12, the flash memory accordingto the present embodiment is provided with an internal power circuitwhich generates a high voltage used for writing or erasure, an inputbuffer circuit which takes in or captures each command inputted fromoutside, an output buffer circuit for outputting a data signal read fromthe memory array and the contents of an internal register to theoutside, an input buffer circuit which takes in an address signal and awrite data signal inputted from outside, etc.

In a manner similar to the embodiment of FIG. 12, the embodiment shownin FIG. 13 is one in which a self-test circuit similar to the testcircuit on the burn-in board described in the above embodiment isprovided within the flash memory. The difference between the embodimentshown in FIG. 12 and the embodiment shown in FIG. 13 resides in that theinformation about each failure address obtained by the test is stored inthe SRAM in the embodiment shown in FIG. 12, whereas in the embodimentshown in FIG. 13, part of a memory array 10 comprising nonvolatilestorage elements is used as a non-failure/failure information storagearea. Since one originally provided with an area (e.g., 64 bytes) forstoring sector management information for each sector of the memoryarray is known as the flash memory, the flash memory can be configuredso as to store non-failure/failure information in such a sectormanagement area 10A.

In the flash memories shown in FIGS. 12 and 13, a function testincluding a write test for writing data into the corresponding memoryarray while updating at least each address can be performed withoutusing a memory tester having a high function. The function test can becarried out within the burn-in apparatus according to the input of eachsignal from the control device of the burn-in apparatus. Further, thefunction test can also be performed using a simple test device otherthan the burn-in apparatus.

Incidentally, while the flash memory has been described as a binarymemory for causing one memory cell to store 1-bit data, i.e., a memoryfor causing one memory cell to store either a logical “1” or a logical“0” in the present specification, the present invention is not limitedto it. In a high-capacity flash memory, the development of amulti-valued technology for causing one memory cell to store data of 2bits to a plurality of bits has been actively performed in recent years.It is needless to say that the present invention can be applied even tosuch a multi-valued memory.

While the invention developed above by the present inventors has beendescribed specifically based on the illustrated embodiments, the presentinvention is not limited to the embodiments. It is needless to say thatvarious changes can be made thereto within the scope not departing fromthe substance thereof. While, for example, the above embodiment hasdescribed, as on example, a case in which the test circuit provided onthe burn-in board is configured using the FPGA, the test circuit can bealso configured using a gate array or an ASIC (special-purpose IC) as analternative to the FPGA.

In the above embodiment, the failure address storage memory 120 isconfigured such that the sector for each tested device 200 and itscorresponding address of the failure address storage memory 120 are in aone-to-one correspondence with each other. Further, the failure addressstorage memory 120 is configured so as to store information indicativeof non-failure/failure therein in association with the correspondingsector. However, the failure address storage memory 120 may beconfigured so as to store an address indicative of a failure or badsector. Alternatively, the failure address storage memory 120 may storefailures in word, byte or bit units other than in sector units.

INDUSTRIAL APPLICABILITY

While the above description has principally been made of, as an example,the test of the flash memory which belongs to the field of applicationcorresponding to the background of the invention, the present inventionis not necessarily limited to it. The present invention can be used evenin the test of a nonvolatile memory other than the flash memory, avolatile memory such as a RAM or the like, and a semiconductorintegrated circuit with those built therein.

1. A method of testing a plurality of semiconductor memories to betested, comprising: mounting the plurality of semiconductor memories ona printed board equipped with a plurality of sockets in which theplurality of semiconductor memories are mountable, and testing circuitseach including a comparator for comparing data read from thesemiconductor memories with expected value data and thereby detectingcoincidences/non-coincidences therebetween and a counter for countingthe number of the detected non-coincidences; connecting the printedboard to a connector lying within a heating chamber of a burn-inapparatus; simultaneously testing the plurality of semiconductormemories by the testing circuits while updating addresses; and countingthe number of addresses at which failures are detected by the counterand outputting the result of counting thereby. 2-25. (cancelled)